1. Field of the Invention
This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to the art of erasing microelectronic flash Electrically Erasable Programmable Read-Only Memory devices which raises threshold voltages of erased cells having threshold voltages below a pre-defined minimum threshold voltage to above this pre-defined minimum threshold voltage after erase verify.
2. Description of the Prior Art
A microelectronic flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) device includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory device are made small by omitting transistors known as select transistors that enable the cells to be erased independently. As a result, all of the cells must be erased together as a block.
A flash memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, a drain, a floating gate and a control gate to which various voltages are applied to program the cell with a binary 1 or 0, to erase all of the cells as a block, to read the cell, to verify that the cell is erased or to verify that the cell is not overerased.
The memory cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of all the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying a voltage, typically 9 volts to the control gate, applying a voltage of approximately 5 volts to the drain and grounding the source causing hot electrons to be injected from a drain depletion region in to the floating gate. Upon removal of the respective programming voltages, the injected electrons are trapped in the floating gate creating a negative charge therein that increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
A cell is read by applying typically 4 volts to the wordline to which the control gate of the cell is connected, applying 1 volt to the bitline to which the drain of the cell is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 volts)1, the bitline current will be zero or at least relatively low. If the cell is not programmed or erased the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float erases a cell. These applied voltages cause the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source, In another arrangement, applying a negative voltage on the order of -10 volts to the control gate, applying 5 volts to the source and allowing the drain to float also erases a cell. A further method of erasing a cell is by applying 5 V to the P-well and -10 V to the control gate while allowing the source/drain to float.
A problem with the conventional flash EEPROM cell arrangement is that due to manufacturing tolerances, some cells become over-erased before other cells are sufficiently erased. The floating gates of the over-erased cells are depleted of electrons and become positively charged. The over-erased cells function as depletion mode transistors that cannot be turned off by normal operating voltages applied to their control gates. The cells functioning as depletion mode transistors introduce leakage current during subsequent program and read operations.
More specifically, during program and read operations only one wordline connected to the control gates of a row of cells is held high at a time, while the other wordlines are grounded. A positive voltage is applied to the drains of all of the cells and if the threshold voltage of an unselected cell is zero or negative, the leakage current will flow through the source, channel and drain of the cell.
The undesirable effect of the leakage current from the over-erased cells is as follows. In a typical flash EEPROM, the drains of a large number of memory transistor cells, for example 512 transistor cells are connected to each bitline. If a substantial number of cells on the bitline are drawing background leakage current, the total leakage current on the bitline can exceed the cell read current. This makes it impossible to read the state of any cell on the bitline and therefore renders the memory inoperative.
Because the background leakage current of a cell varies as a function of threshold voltage, the lower (more negative) the threshold voltage the higher the leakage current. It is therefore desirable to prevent cells from being over-erased and reduce the threshold voltage distribution to as low a range as possible, with ideally all cells having the same threshold voltage after erase on the order of 2 volts.
It is known in the art to reduce the threshold voltage distribution by performing an over-erase correction operation, which reprograms the most over-erased cells to a higher threshold voltage. An over-erase correction operation of this type is generally known as Automatic Programming Disturb (APD).
An APD method referred to as Automatic Programming Disturb Erase (APDE) is disclosed in U.S. Pat. No. 5,642,311, entitled "OVERERASE CORRECTION FOR FLASH MEMORY WHICH LIMITS OVERERASE AND PREVENTS ERASE VERIFY ERRORS," issued Jun. 24, 1997, to Lee Cleveland. This patent is assigned to the same assignee as the present invention and is incorporated herein by reference in its entirety. The method includes sensing for over-erased cells and applying programming pulses thereto, which bring their threshold voltages back up to acceptable values.
Following application of an erase pulse, under-erase correction is first performed on a cell-by-cell basis by rows. The cell in the first row and column position is addressed and erase verified by applying 4 volts to the control gate (wordline), 1 volt to the drain (bitline), grounding the source, and using sense amplifiers to sense the bitline current to determine if the threshold voltage of the cell is above a value of, for example, 2 volts. If the cell is under-erased, indicated by a threshold voltage above 2 volts, the bitline current will be low. In this case, an erase pulse is applied to all of the cells, and the first cell is erase verified again.
In the method described in U.S. Pat. No. 5,642,311, after application of each erase pulse and prior to a subsequent erase verify operation, over-erase correction is performed on all the cells in the memory. Over-erase verification is performed on the bitlines of the array or memory in sequence by grounding the wordlines, applying typically 1 volt to each bitline in sequence and sensing the bitline current. If the bitline current is above a predetermined value at least one of the cells connected to the bitline is over-erased and is drawing leakage current. In this case, an over-erase correction pulse is applied to the bitline. The over-erase correction pulse is a pulse of approximately 5 volts applied to the bitline for a predetermined length of time, typically 100 .mu.s.
After application of the over-erase correction pulse to the bitline, the cells on the bitline are over-erase verified again. If the bitline current is still high indicating that an over-erased cell still remains connected to the bitline, another over-erase correction pulse is applied to the bitline. This procedure is repeated, as many times as necessary until the bitline current is reduced to the predetermined value that is lower than the read current. Then, the procedure is performed for the rest of the cells in the first row and following rows until all of the cells in the memory have been erase verified.
By performing the over-erase correction procedure after each erase pulse, the extent to which cells are over-erased is reduced, improving the endurance of cells. Further, because over-erased cells are corrected after each erase pulse bitline leakage current is reduced during erase verify, thus preventing under-erased cells from existing upon completion of the erase verify procedure.
In U.S. Pat. No. 5,359,558 issued on Oct. 25, 1994, to Chung K. Chang et al. and entitled "Flash EEPROM Array with Improved High Endurance," there is disclosed an over-erased bit correction structure which includes sensing circuitry for detecting column leakage indicative of an over-erased bit during an APDE mode of operation and a pulse counter for applying program pulses so as to program back the over-erased memory cells. Further, in U.S. Pat. No. 5,875,130 issued on Feb. 23, 1999, to Sameer S. Haddad et al. and entitled "Method for Programming Flash Electrically Erasable Programmable Read-Only Memory," there is disclosed an overerase correction procedure which includes applying an operational pulse to a cell and applying a bias voltage between the source and substrate of the cell while the operational pulse is being applied. The operational pulse can be an overerase correction pulse or a programming pulse.
U.S. Pat. No. 5,901,090 issued on May 4, 1999, to Sameer S. Haddad et al. and entitled "Method for Erasing Flash Electrically Erasable Programmable Read-Only Memory (EEPROM)," teaches an overerase correction or soft programming procedure which includes applying an erase pulse to a plurality of cells and applying overerase correction pulses to the plurality of cells so that the threshold voltages of all cells will be above a V.sub.T LOW. In addition, there is taught in U.S. Pat. No. 6,011,721 issued on Jan. 4, 2000, to Ravi S. Sunkavalli and entitled "Method for Sensing State of Erasure of Flash Electrically Erasable Programmable Read-Only Memory (EEPROM)" a sensing procedure which enables accurate calculation of the state of erasure of the memory cells as a predetermined function of a sensed source voltage. The '558, '130, '090 and '721 patents are all assigned to the same assignee as the present invention and are incorporated herein by reference in their entirety.
Furthermore, in U.S. Pat. No. 5,912,845 issued on Jun. 15, 1999, to Chia-Shing Chen et al. and entitled "Method and Circuit for Substrate Current Induced Hot E Injection (SCIHE) Approach for VTConvergence at Low V.sub.cc Voltage" there is disclosed a method for soft programming memory cells in a floating gate memory device which includes a soft program to generate pulses for quickly repairing over-erased cells and for limiting the amount of current generated during the process. During the soft programming, a gate voltage, a drain voltage, and a well voltage are applied to the control gate, drain, and well, respectively. An active limiter is coupled to the source in order to render a high efficiency for the soft programming process. This '845 patent is likewise incorporated herein by reference in its entirety.
The erase scheme of the present invention represents a significant improvement over the aforementioned '558, '130, '090, '721, and '845 patents by preventing false erase verify readings and tightening the threshold voltage distribution of the memory cells after erase. This is achieved in the instant invention by combining optimally the features of the automatic program disturb erase (APDE) mode of operation and the soft programming technique.